In recent years, size-reduction, enhancement for function, higher integration degree and multiple pin arrangement have been progressed remarkably for IC package. Further, CSP as a package of a size identical with a chip-size has been developed recently.
JP-A-11-121507 proposes a method of packaging in a state of wafer and fabricating a chip-size package. However, in this method, bumps for connecting an IC package with the outside are formed at electrode positions in IC. In recent tend for the reduction of chip-size and multiple pin arrangement, the pitch for arranging electrodes of the chip has been narrowed more and more and it is necessary to re-arrange the electrodes on the IC chip to expand the electrode pitch for facilitating subsequent mounting.
This invention intends to solve the foregoing problems in the prior art and provide a method of fabricating a chip-size package in which the electrode pitch is extended by forming conductor wirings on the side of the electrode forming surface of a semiconductor element efficiently and at a reduced cost and, particularly, to provide a method capable of forming wirings and bumps easily.